FPGA Verification

This role is for one of Weekday’s clients

Min Experience: 15+ years
Location: Bengaluru
JobType: full-time

Provide technical leadership and architectural oversight for the pre-silicon verification, emulation prototyping, and post-silicon validation of complex, high-throughput FPGA systems designed for Data Center acceleration, AI workloads, and cloud infrastructure. You will define the global verification strategy, architect end-to-end UVM frameworks, and lead the validation of cutting-edge Network-on-Chip (NoC) systems and high-speed interfaces to ensure zero-defect hardware deployment. 

Requirements

Desired Skills:

• Extensive experience leading the design, development, functional verification, and post-silicon validation of complex FPGAs.
• Expert-level RTL development and advanced constrained-random verification architectures using VHDL / Verilog / SystemVerilog.
• Deep structural and architectural familiarity with high-density AMD (Xilinx) UltraScale+ / Versal and Intel (Altera) Stratix / Agilex FPGAs.
• Mastery of modern and legacy FPGA toolchains including Xilinx Vivado, ISE, and Intel Quartus Prime. Proven track record architecting complex functional verification environments in ModelSim, QuestaSim, or VCS, with mastery of UVM / OVM methodologies.
• Hands-on experience architecting emulation and prototyping solutions (e.g., ZeBu, Palladium, Protium, HAPS) for complex SOC/FPGA designs, early OS/software integration, and co-emulation.
• Expertise in leading physical lab bring-up, silicon debugging, and driving test automation strategy using Python / Tcl alongside high-speed test equipment.
• Demonstrated ability to drive technical roadmaps, mentor mid-to-senior engineers, and collaborate across RTL design, software, and systems engineering teams.
• Deep verification and validation experience with high-speed interfaces (e.g., PCIe Gen 5/6, CXL, 100G/400G Ethernet, HBM2e/3, DDR5) and advanced Network-on-Chip (NoC) topologies optimized for low-latency Data Center workloads.

Must-have skills

FPGA design, functional verification, post-silicon validation